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NEW QUESTION: 1
You are a portfolio manager at an organization that uses Project Server 2013.
You supervise five very large projects. Each project has its own project manager and a project team with many resources. One of your main activities is reviewing all documentation of the five projects. The project teams are constantly updating and publishing new documents in the Project Site of each project.
You need to implement an information review process that meets the following requirements:
Receive a notification every time a document is updated or published in the Project Sites.
Have a centralized way to view the notifications.
Implement the process in the least amount of time.
What should you do?
A. Ask the project managers and the project teams to send you an email every time they update or create a new element in the project site. Review your inbox periodically for notifications from the project team.
B. Go to Project Site of each project and select the Follow site option. Review your Newsfeed periodically for news about the Project Sites.
C. Go to Project Site of each project and select the Follow option for each published document. Review your Newsfeed periodically for news about the documents.
D. Go to the User page of each member from the five project teams and select the Follow user option.
Review your Newsfeed periodically for news about each user.
Answer: B
NEW QUESTION: 2
You would like to associate a profile called ip-info with a PPPoE interface operating on FastEthernet 3/1.200. Which set of configuration commands accomplishes this goal?
A. subinterface fastethernet 3/1.200.1 profile ip-info
B. pppoe subinterface fastethernet 3/1.200.1 profile ip-info
C. pppoe interface fastethernet 3/1.200.1 profile ip-info
D. pppoeinterface fastethernet 3/1.200.1 profile ip-info
Answer: B
NEW QUESTION: 3
Which of the following describes a computer processing architecture in which a language compiler or pre- processor breaks program instructions down into basic operations that can be performed by the processor at the same time?
A. Reduced-Instruction-Set-Computer (RISC)
B. Super Scalar Processor Architecture (SCPA)
C. Complex-Instruction-Set-Computer (CISC)
D. Very-Long Instruction-Word Processor (VLIW)
Answer: D
Explanation:
Explanation/Reference:
Explanation:
Very long instruction word (VLIW) describes a computer processing architecture in which a language compiler or pre-processor breaks program instruction down into basic operations that can be performed by the processor in parallel (that is, at the same time).
These operations are put into a very long instruction word which the processor can then take apart without further analysis, handing each operation to an appropriate functional unit. The following answer are incorrect: The term "CISC" (complex instruction set computer or computing) refers to computers designed with a full set of computer instructions that were intended to provide needed capabilities in the most efficient way.
Later, it was discovered that, by reducing the full set to only the most frequently used instructions, the computer would get more work done in a shorter amount of time for most applications. Intel's Pentium microprocessors are CISC microprocessors. The PowerPC microprocessor, used in IBM's RISC System/6000 workstation and Macintosh computers, is a RISC microprocessor. RISC takes each of the longer, more complex instructions from a CISC design and reduces it to multiple instructions that are shorter and faster to process.
RISC technology has been a staple of mobile devices for decades, but it is now finally poised to take on a serious role in data center servers and server virtualization. The latest RISC processors support virtualization and will change the way computing resources scale to meet workload demands. A superscalar CPU architecture implements a form of parallelism called instruction level parallelism within a single processor. It therefore allows faster CPU throughput than would otherwise be possible at a given clock rate. A superscalar processor executes more than one instruction during a clock cycle by simultaneously dispatching multiple instructions to redundant functional units on the processor. Each functional unit is not a separate CPU core but an execution resource within a single CPU such as an arithmetic logic unit, a bit shifter, or a multiplier.
References:
http://whatis.techtarget.com/definition/0,,sid9_gci214395,00.html
http://searchcio-midmarket.techtarget.com/definition/CISC
http://en.wikipedia.org/wiki/Superscalar
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